1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device comprising an isolation film formed on a silicon substrate, a floating gate which is formed in an active region isolated by the isolation film and disposed a in gap between adjacent isolation film(s), and a control gate having a region which overlaps one end portion of the floating gate via a tunnel oxide film covering the floating gate, and also to a method of fabricating such a device.
2. Description of the Related Art
In a nonvolatile semiconductor memory device in which each memory cell consists of a single transistor and can be electrically erased, particularly in a programmable ROM (EEPROM: Electrically Erasable and Programmable ROM), each memory cell is formed by a transistor of a double gate structure having a floating gate and a control gate. In such a transistor of a double gate structure, a data is written by injecting hot electrons generated in the channel under the gap region formed by the floating gate and the control gate into the floating gate. The data is erased by extracting charges from the floating gate to the control gate by means of F-N tunneling (Fowler-Nordheim tunneling).
FIG. 10 is a plan view of a memory cell of a nonvolatile semiconductor memory device having a floating gate, and FIG. 11 is a cross sectional view taken along the line X2--X2. These figures show a split gate structure in which a control gate 6 is juxtaposed with a floating gate 4.
In a surface region of a P-type silicon substrate 1, plural isolation films 2 consisting of a LOCOS oxide film which is formed with being selectively thickened by the LOCOS (Local Oxidation Of Silicon) process are formed in a strip-like manner so as to partition the surface region into device regions. Floating gates 4 are arranged on the silicon substrate 1 via an oxide film 3A so as to extend over adjacent isolation films 2. Each of the floating gates 4 is independently formed for each memory cell. A selective oxide film 5 on the floating gate 4 is formed by the selective oxidizing method so as to be thick in a center portion of the floating gate 4, and causes an edge portion of the floating gate 4 to have an acute angle. According to this configuration, during the data erasing operation, the electric field is easily enhanced in the end portion of the floating gate 4.
On the silicon substrate 1 where the plural floating gates 4 are arranged, control gates 6 are arranged via a tunnel oxide film 3 integrated with the oxide film 3A, so as to respectively correspond to the rows of the floating gates 4. Each of the control gates 6 is disposed so that a part of the control gate overlaps the floating gate 4 and the other part is contacted with the silicon substrate 1 via the oxide film 3A. The floating gates 4 and the control gates 6 are arranged so that adjacent rows are symmetrical with respect to plane (i.e., symmetrical with respect to one sectional plane).
N-type drain regions 7 and source regions 8 are formed in substrate regions between adjacent control gates 6 and those between adjacent floating gates 4. Each drain region 7 is independently formed so as to be surrounded by the isolation films 2 between the control gates 6, to each source region 8 is continuous in the direction along with the control gates 6. A memory cell transistor is configured by the floating gate 4, the control gate 6, the drain region 7, and the source region 8.
An aluminum interconnection 10 is disposed over the control gate 6 and floating gate 4 via an oxide film 9 with the angle of 90 degrees to the control gate. The aluminum interconnection 10 is connected to the drain region 7 via a contact hole 11. Each control gate 6 functions as a word line, the source region 8 extending in parallel with the control gate 6 functions as a source line, and the aluminum interconnection 10 connected to the drain region 7 functions as a bit line.
In the memory cell transistor of the double gate structure, the conductance between the source and the drain is varied depending on the amount of charges injected to the floating gate 4. Therefore, charges are selectively injected to the floating gates 4, so that the channel conductance of specific memory cell transistors are varied.
The differences of the operation characteristics of the memory cell transistors caused by the variation are made corresponding to stored data.
In the nonvolatile semiconductor memory device, for example, the operations of writing, erasing, and reading a data are achieved in the following manner. In the writing operation, the potential of the control gate 6 is set to 2 V, that of the drain region 7 is set to 0.5 V, and the high potential of the source region 8 is set to 12 V. As a result, when the high potential is applied to the source region 8, the potential of the floating gate 4 is raised to about 9 V in accordance with the coupling ratio between the source region 8 and the floating gate 4, and hot electrons generated in the vicinity of the channel are accelerated toward the floating gate 4 and then injected to the floating gate 4 via the oxide film 3A, thereby writing a data.
Contrary that, in the erasing operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 14 V. As a result, charges (electrons) accumulated in the floating gate 4 are discharged by means of F-N tunneling from the acute angle portion of the edge portion of the floating gate 4 to the control gate 6 with passing through the tunnel oxide film 3, thereby erasing the data.
In the reading operation, the potential of the control gate 6 is set to 4 V, the drain region 7 is set to 2 V, and the source region 8 is set to 0 V. In this case, when injected charges (electrons) exist in the floating gate 4, the potential of the floating gate 4 is lowered, and hence no channel is formed below the floating gate 4 so that the drain current does not flow. By contrast, when injected charges (electrons) do not exist in the floating gate 4, the potential of the floating gate 4 is raised, and hence a channel is formed below the floating gate 4 so that the drain current flows.
Hereinafter, a method of fabricating the nonvolatile semiconductor memory device will be described. In FIGS. 12 to 17, A is a top view, B is a cross sectional view taken along the line A--A of A, and C is a cross sectional view taken along the line B--B of A.
Referring to FIG. 12, the isolation film 2 is formed on the silicon substrate 1 by the LOCOS process. Namely, as shown in FIG. 12B, a pad oxide film 21 and a pad polycrystalline silicon film 22 are formed on the silicon substrate 1. Thereafter, selective oxidation is conducted with using a silicon nitride film 23 having an opening as a mask, thereby forming the isolation film 2.
Next, as shown in FIG. 13, the pad oxide film 21 and the pad polycrystalline silicon film 22 in the device forming region are removed away. As shown in FIG. 14, thereafter, the upper portion of the silicon substrate 1 is thermally oxidized to form the oxide film 3A, a polycrystalline silicon film 24 is formed on the oxide film, and a silicon nitride film 25 having an opening is then formed.
As shown in FIG. 15, the polycrystalline silicon film 24 is selectively oxidized with using the silicon nitride film 25 as a mask, thereby forming the selective oxide film 5.
Thereafter, as shown in FIG. 16, the silicon nitride film 25 is removed away, and the polycrystalline silicon film 24 is then etched with using the selective oxide film 5 as a mask, thereby forming the floating gate 4.
As shown in FIG. 17, the tunnel oxide film 3 is formed (on the entire face), a conductive film consisting of a polycrystalline silicon film and a tungsten silicide film is then formed, and the conductive film is patterned to form the control gate 6. Alternatively, the control gate 6 may be a single-layer film consisting of a polycrystalline silicon film.
Although the description is omitted, as shown in FIGS. 10 and 11, the source region 8 and the drain region 7 are then formed so as to form a memory cell of the nonvolatile semiconductor memory device.
However, such a nonvolatile semiconductor memory device has the following problem. As shown in FIG. 18 (which is an enlarged view of a part of FIG. 17B), the control gate 6 covering the floating gate 4 which overrides an end portion of the isolation film 2 is sharpened in a horn-like manner (see A in the circle of a broken line shown in FIG. 18), and the electric field is concentrated in the portion. Therefore, the dielectric strength between the floating gate 4 and the control gate 6 is lowered, so that a so-called reverse tunneling failure easily occurs.
The memory device has a further problem in that a high accuracy is required in alignment of the floating gate 4 and the isolation film 2. When mask misalignment once occurs between the mask for forming the isolation film and that for forming the floating gate, an end portion of the floating gate 4 cannot overlap the isolation film 2, or the degree of overlap is small (see FIG. 19).
In such a case that in an end portion of the floating gate 4 cannot overlap the isolation film 2, or the degree of overlap is small in a region, even if in the reading operation, the floating gate is in a written state (in which electron is accumulated) and drain current properly does not flow in the channel region, for example, a leak current flows from the source region 8 toward the drain region 7 as shown in FIG. 19 (see the arrow I.sub.L in the figure). As a result, there arises a problem in that it is judged that the memory cell is in the erased state.
When, in order to cope with the problem, the size of the floating gate is increased, there arises a problem in that adjacent floating gates are contacted with each other because the gap between adjacent floating gates is very narrow as shown in FIG. 10.